This invention relates to staging of data into a cache memory from a disk track in response to a host processor read command and, more particularly, to a method and apparatus for enabling a read-out of requested blocks of data from the cache memory prior to completion of the staging of an entire track of data from the disk track.
Modern disk subsystems provide mass storage facilities for plural host processors. Storage controllers associated with such disk subsystems enable a staging of data from disk tracks into a cache memory, either in response to a read request or, in anticipation of a read request. Early cache memory management systems did not enable a read-out of track data being stored therein, until the entire track had been transferred from disk. This was so even though the requested data might have been positioned at the beginning of the track and been resident in cache memory for a period of time, awaiting completion of the track transfer.
More recent cache memory controllers have enabled concurrent input and output operations from the cache memory. In particular, they enable transfer of data in the cache memory to the requestor while further track data is still being written into the cache memory. Examples of such prior art systems appear in the patents described below.
U.S. Pat. No. 5,121,479 to O""Brien describes a system for coordinating reading and writing of data files into and out of a data buffer so that a data file can be written into the data buffer while another data file is concurrently being read out of the data buffer. U.S. Pat. No. 5,689,729 to Inoue describes a storage subsystem which provides plural access paths to a cache memory from a host processor and a plurality of independent access paths between the cache memory and a disk memory. Means are described which allow substantially independent operation of the host-to-cache paths and the cache-to-disk paths.
U.S. Pat. No. 4,800,483 to Yamamoto et al. describes a system which enables data transfer operations to be executed in parallel, between a disk unit and disk cache unit, and between the disk cache unit and a main storage memory.
In summary, each of the aforesaid patents allows overlapping input and output of data to/from a cache memory to reduce latency time that is incurred during such data transfers.
A subset of the prior art enables a readout of a data record from cache memory, even before the entire data record has been received into the cache memory. For instance, U.S. Pat. No., 5,742,789 to Ofer et al. describes a system for retrieving a data file from a disk drive and provides for overlapping read operations, thereby reducing latency seen by a requesting host computer. Upon receiving a request for retrieval of data, a channel director places the request in a data cache. If a cache miss occurs, a disk director reads and transfers the data file from the disk drive to the data cache. At a certain point in the transfer of the data file into the data cache, the disk director places a start read message in the data cache which is then read by the channel director. Upon receipt of the start read message, the channel director begins to read the data file from the data cache, thus reading data from the data cache as the disk director completes writing the data file to the data cache.
U.S. Pat. No. 5,353,426 to Patel et al. applies the above technique of Ofer et al. to the obtaining of instructions for a currently running program on a processor. More specifically, Patel et al. provide a cache miss buffer which is adapted to satisfy read requests to a portion of a cache fill that is still in progress, without waiting for the cache fill to complete. Patel et al. try to avoid an instruction/data fetch fault which would cause a central processing unit to become idle while awaiting the receipt of the instruction/data. More specifically, the system of Patel et al. determines if the address requested to be accessed is part of a memory block frame within a current cache fill and, if yes, control logic enables a transfer thereof out of cache, even though the cache fill is not yet complete.
In accordance with the above prior art teachings, a read command which requires a staging of a subset of data from a track into cache memory, upon sensing a last data block of a requested set of data blocks being written into cache memory, will signal a cache memory output control mechanism to commence outputting the data to the requesting host processor.
In many instances, it is desirable to read the entire disk track into cache memory so that if a succeeding set of data blocks from the track is requested next, or if an update command for data in the track is received, that the track is already present in the cache memory. Accordingly, many read commands require that the entire track be staged into cache memory and, upon sensing the completion of the track staging operation, then enable a cache memory controller to access the requested data. More specifically, the command is set up in such a manner that a data access can occur only when the requested data transfer is complete (in many cases being the entire track).
Accordingly, it is an object of this invention to provide an improved method and apparatus for reducing latency time experienced in response to a disk track read request.
The invention enables reduction of latency time for receipt of data which has been requested from a disk system. The method enables use of a read command which enables a cache memory output to occur only when the read command has been completed. The method of the invention initially receives a read request from a host processor for a number of data blocks on a disk track (referred to as requested blocks), the requested blocks being a subset of blocks stored in the disk track. If the requested blocks are not already stored in a cache memory, the method constructs at least a first command to transfer the track to cache memory, the first command enabling identification of a last data block of the requested blocks. A second command is also prepared to transfer the track to cache memory, the second command enabling identification of the last. block of the remaining set of blocks in the track. Thereafter, the first command is executed and when the last block of the requested blocks has been transferred to cache memory, indicating completion of the first command, transfer of the requested blocks from cache memory to the host processor is commenced. The second command is also executed and enables a staging of the remaining blocks of the disk track to cache memory, thereby assuring that the entire track resides in cache memory.